The present disclosure relates to a control device, a storage device, and a data writing method, and particularly to a writing control with respect to a non-volatile memory performing multi-value storage with 2 bits or more in a memory cell.
For example, a storage device using a non-volatile memory such as a NAND type flash memory is widely used. The non-volatile memory is used for a memory card, a solid state drive (SSD), an embedded multimedia card (eMMC) and the like which are used for various electronic apparatuses, information processing apparatuses or the like, for example.
Japanese Unexamined Patent Application Publication Nos. 2009-70098, 2007-334852, 2007-193838, and 2007-58840 disclose the storage devices using the flash memory.
In addition, for example, it is known that the NAND type flash memory or the like includes a single level cell (SLC) which determines a storage amount of electrons (charge amount) within a floating gate of one cell using one threshold value and thus stores one bit of information, and additionally includes a multi level cell (MLC) which determines a charge amount difference using multi-values with 4 pieces or more and thus stores two or more bits of information.
In addition, there is also a case where a cell storing 2 bits is particularly indicated by the MLC in a narrow sense, and a cell storing 3 bits is called a triple level cell (TLC).
Japanese Unexamined Patent Application Publication Nos. 2010-198407 and 2007-94921 disclose a multi-value flash memory which stores multiple bit data in one cell.
A physical block address (PBA: Physical Address) is used as an address of a physical storage area in such a NAND type flash memory or the like. Therefore, a physical block, a physical page, and a physical sector are set. The physical page is configured to have multiple physical sectors, and the physical block is configured to have multiple physical pages.
Erasing can be performed by a physical block unit, and writing (programming) and reading can be performed by a physical page unit.
For an address designation from a host side or a memory control unit side, a logical block address (LBA: Logical Address) is used. A logical block and a logical page which use the logical address, are associated with a physical address. Therefore, when there is an access request, the logical address is converted into the physical address, and an access to an actual flash memory is performed.
In a case of the multi-value NAND type flash memory, an upper level page and a lower level page are set as the physical page in which the physical address is provided.
For example, in a case of the MLC storing 2 bits, a lower page is set as the lower level page, and an upper page is set as the upper level page.
In a case of the TLC storing 3 bits, the lower page is set as the lower level page, a Middle Page is set as a middle level page, and the upper page is set as the upper level page.